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integrated silicon solution, inc. 1 rev.? f 09/28/2010 is61(64)lf12832a??is64vf12832a is61(64)lf12836a??is61(64)vf12836a is61(64)lf25618a??is61(64)vf25618a copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? burst sequence control using mode input ? three chip enable option for simple depth expan- sion and address pipelining ? common data inputs and data outputs ? auto power-down during deselect ? single cycle deselect ? snooze mode for reduced-power standby ? power supply lf: v dd 3.3v + 5%, v ddq 3.3v/2.5v + 5% vf: v dd 2.5v -5% +10%, v ddq 2.5v -5% +10% ? jedec 100-pin tqfp, 119-pin pbga, and 165- pin pbga packages ? automotive temperature available ? lead-free available septebmer?2010 128k?x?32, ?128k?x?36, ?256k?x?18? 4?mb? synchronous? flow-through? static?ram description the issi is61(64)lf12832a, is64vf12832a, is61(64) lf/vf12836a and is61(64)lf/vf25618a are high-speed, low-power synchronous static rams designed to provide burstable, high-performance memory for communication and networking applications. the is61(64)lf12832a is organized as 131,072 words by 32 bits. the is61(64)lf/ vf12836a is organized as 131,072 words by 36 bits. the is61(64)lf/vf25618a is organized as 262,144 words by 18 bits. fabricated with issi 's advanced cmos technol- ogy, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write en- able (bwe) input combined with one or more individual byte write signals (bwx ). in addition, global write (gw) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be gener- ated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left foating. fast ? access? time ? symbol? parameter ? -6.5? -7.5? units t kq clock access time 6.5 7.5 ns t kc cycle time 7.5 8.5 ns frequency 133 117 mhz
2 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a block diagram 17/18 binary counter gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 15/16 17/18 address register ce d clk q dq(a-d) byte write registers d clk q enable register ce d clk q bwe bw(a-d) x18: a,b x32/x36: a-d ce ce2 ce2 128kx32; 128kx36; 256kx18 memory array 32, 36, or 18 input registers clk oe 2/4/8 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a power down zz
integrated silicon solution, inc. 3 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a b ottom view b ottom view 165-pin?bga 165-ball, 13x15 mm bga 119-pin?bga 119-ball, 14x22 mm bga
4 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 119 bga package pin configuration 128k x 36 (top view) pin?descriptions 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc ce2 a adsc a ce2 nc c nc a a v dd a a nc d dqc dqpc vss nc vss dqpb dqb e dqc dqc vss ce vss dqb dqb f v ddq dqc vss oe vss dqb v ddq g dqc dqc bwc adv bwb dqb dqb h dqc dqc vss gw vss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd vss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd vss bwe vss dqa v ddq n dqd dqd vss a 1 * vss dqa dqa p dqd dqpd vss a 0 * vss dqpa dqa r nc a mode v dd nc a nc t nc nc a a a nc zz u v ddq nc nc nc nc nc v ddq symbol? pin?name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce, ce2, ce2 synchronous chip select bwx (x=a-d) synchronous byte write controls bwe byte write enable symbol? pin?name oe output enable zz power sleep mode mode burst sequence selection nc no connect dqa-dqd data inputs/outputs dqpa-pd output power supply v dd power supply v ddq output power supply vss ground note: ? * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired.
integrated silicon solution, inc. 5 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 119 bga package pin configuration 256k x 18 (top view) pin?descriptions note: ? * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. symbol? pin?name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce, ce2, ce2 synchronous chip select bwx (x=a,b) synchronous byte write controls bwe byte write enable symbol? pin?name oe output enable zz power sleep mode mode burst sequence selection nc no connect dqa-dqb data inputs/outputs dqpa-pb output power supply v dd power supply v ddq output power supply vss ground 1 2 3 4 5 6 7 ??????? a v ddq a a adsp a a v ddq b nc ce2 a adsc a ce2 nc c nc a a v dd a a nc d dqb nc vss nc vss dqpa nc e nc dqb vss ce vss nc dqa f v ddq nc vss oe vss dqa v ddq g nc dqb bwb adv vss nc dqa h dqb nc vss gw vss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk vss nc dqa l dqb nc vss nc bwa dqa nc m v ddq dqb vss bwe vss nc v ddq n dqb nc vss a 1 * vss dqa nc p nc dqpb vss a 0 * vss nc dqa r nc a mode v dd nc a nc t nc a a nc a a zz u v ddq nc nc nc nc nc v ddq
6 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a pin?descriptions 165 pbga package pin configuration 128k x 36 (top view) note: ? * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 bwe adsc adv a nc b nc a ce2 bwd bwa clk gw oe adsp a nc c dqpc nc v ddq vss vss vss vss vss v ddq nc dqpb d dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb e dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb f dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb g dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb h nc nc nc v dd vss vss vss v dd nc nc zz j dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa k dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa l dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa m dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa n dqpd nc v ddq vss nc nc nc vss v ddq nc dqpa p nc nc a a nc a 1 * nc a a a nc r mode nc a a nc a 0 * nc a a a a symbol? pin?name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce, ce2, ce2 synchronous chip select bwx (x=a,b,c,d) synchronous byte write controls symbol? pin?name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection nc no connect dqx data inputs/outputs dqpx data inputs/outputs v dd 3.3v/2.5v power supply v ddq isolated output power supply 3.3v /2.5v vss ground
integrated silicon solution, inc. 7 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a note: ? * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 165 pbga package pin configuration 256k x 18 (top view) pin?descriptions 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwb nc ce2 bwe adsc adv a a b nc a ce2 nc bwa clk gw oe adsp a nc c nc nc v ddq vss vss vss vss vss v ddq nc dqpa d nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa e nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa f nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa g nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa h nc nc nc v dd vss vss vss v dd nc nc zz j dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc k dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc l dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc m dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc n dqpb nc v ddq vss nc nc nc vss v ddq nc nc p nc nc a a nc a 1 * nc a a a nc r mode nc a a nc a 0 * nc a a a a symbol? pin?name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce, ce2, ce2 synchronous chip select bwx (x=a,b) synchronous byte write controls symbol? pin?name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection nc no connect dqx data inputs/outputs dqpx data inputs/outputs v dd 3.3v/2.5v power supply v ddq isolated output power supply 3.3v/2.5v vss ground
8 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a dqpb dqb dqb vddq vss dqb dqb dqb dqb vss vddq dqb dqb vss nc vdd zz dqa dqa vddq vss dqa dqa dqa dqa vss vddq dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a dqpc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 46 47 48 49 50 pin?descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa-bwd synchronous byte write enable bwe synchronous byte write enable ce, ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpd parity data input/output gw synchronous global write enable mode burst sequence mode selection oe output enable v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v vss ground zz snooze enable pin configuration (3? chip-enable?option)? 100-pin? tqfp?(128k?x?36) nc dqb dqb vddq vss dqb dqb dqb dqb vss vddq dqb dqb vss nc vdd zz dqa dqa vddq vss dqa dqa dqa dqa vss vddq dqa dqa nc a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 46 47 48 49 50 100-pin? tqfp?(128k?x?32) (3? chip-enable?option)?
integrated silicon solution, inc. 9 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a pin configuration (3? chip-enable?option) pin?descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa-bwb synchronous byte write enable bwe synchronous byte write enable ce, ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqb synchronous data input/output dqpa-dqpb parity data i/o; dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 gw synchronous global write enable mode burst sequence mode selection oe output enable v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v vss ground zz snooze enable 100-pin? tqfp?(256k?x?18) a nc nc vddq vss nc dqpa dqa dqa vss vddq dqa dqa vss nc vdd zz dqa dqa vddq vss dqa dqa nc nc vss vddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc nc nc vddq vss nc nc dqb dqb vss vddq dqb dqb nc vdd nc vss dqb dqb vddq vss dqb dqb dqpb nc vss vddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 46 47 48 49 50
10 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a partial ? truth ? table function? gw bwe b wa bwb bwc bwd read h h x x x x read h l h h h h write byte 1 h l l h h h write all bytes h l l l l l write all bytes l x x x x x truth ? table (1-8) operation ? address? ce? ce2 ? ce2? zz ? adsp? adsc? adv? write? oe ? clk? dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: ? 1. x means dont care. h means logic high. l means logic low. 2. for write, l means one or more byte write enable signals (bwa-d) and bwe are low or gw is low. write = h for all bwx, bwe, gw high. 3. bwa enables writes to dqas and dqpa. bwb enables writes to dqbs and dqpb. bwc enables writes to dqcs and dqpc. bwd enables writes to dqds and dqpd. dqpa and dqpb are available on the x18 version. dqpa-dqpd are avail- able on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarifcation.
integrated silicon solution, inc. 11 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a interleaved ? burst?address? table ?(mode?=? v dd or?no?connect) ? external? address? 1st? burst? address? 2nd? burst? address? 3r d? burst? address ? a1? a0 ? a1? a0 ? a1? a0 ? a1? a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear? burst?address? table ?(mode?=? vss) ? ? ? 0,0 1,0 0,1 a1', a0' = 1,1 absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit t stg storage temperature C55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to vss for i/o pins C0.5 to v ddq + 0.5 v v in voltage relative to vss for C0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to vss C0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma - nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric felds; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
12 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a dc?electrical? characteristics? (over operating range) ? 3.3v? 2.5v ? symbol? parameter ? test ?conditions? min. ? max. ? min. ? max. ? unit ? v oh output high voltage i oh = C4.0 ma (3.3v) 2.4 2.0 v i oh = C1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) 0.4 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage C0.3 0.8 C0.3 0.7 v i li input leakage current v ss v in v dd (1) C5 5 C5 5 a i lo output leakage current v ss v out v ddq , oe = v ih C5 5 C5 5 a operating ?range?(is61/64lfxxxxx) ? range ? ambient? temperature ? v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v/2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v/2.5v 5% automotive -40c to +125c 3.3v 5% 3.3v/2.5v 5% operating ?range?(is61/64vfxxxxx) ? range ? ambient? temperature ? v dd v ddq commercial 0c to +70c 2.5v -5% +10% 2.5v -5% +10% industrial -40c to +85c 2.5v -5% +10% 2.5v -5% +10% automotive -40c to +125c 2.5v -5% +10% 2.5v -5% +10%
integrated silicon solution, inc. 13 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a power ? supply? characteristics (1) ? (over operating range) ? ???????????6.5? ? 7.5 ? ??????????????max ????????????????????????????? ? max ? symbol? parameter ? test ?conditions? temp. ? range?? x18? x32/x36 ? ? x18? x32/x36? uni t ? i cc ac operating device selected, com. 175 175 155 155 ma supply current oe = v ih , zz v il , ind. 180 180 160 160 all inputs 0.2v or v dd C 0.2v, a u to . 190 190 175 175 cycle time t kc min. typ. (2) 120 110 i sb standby current device deselected, com. 90 90 90 90 ma ttl input v dd = max., ind. 100 100 100 100 all inputs v il or v ih , auto. 120 120 120 120 zz v il , f = max. i sbi standby current device deselected, com. 70 70 70 70 ma c mos input v dd = max., ind. 75 75 75 75 v in v ss + 0.2v or v dd C 0.2v auto. 90 90 90 90 f = 0 typ. 40 40 i sb 2 sleep mode zz>v ih com. 30 30 30 30 ma ind. 35 35 35 35 auto. 45 45 45 45 typ. 25 25 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100 a maximum leakage current when tied to v ss + 0.2v or v dd C 0.2v. 2. typical values are measured at v dd = 3.3v, t a = 25 o c and not 100% tested. capacitance (1,2) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 3.3v.
14 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 3.3v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac ? test? loads figure?2 317 5 pf including jig and scope 351 output 3.3v figure?1 output z o = 50 1.5v 50
integrated silicon solution, inc. 15 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 2.5v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure?3 figure?4 2.5v?i/o?output? load? equivalent
16 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a read/write?cycle?switching? characteristics (1) ? (over operating range) ? ? ? ?6.5? ??7.5 ? symbol? parameter ? min. ? max. ? min. ? max. ? unit fmax clock frequency 133 117 mhz t kc cycle time 7.5 8.5 ns t kh clock high time 2.2 2.5 ns t kl clock low time 2.2 2.5 ns t kq clock access time 6.5 7.5 ns t kqx (2) clock high to output invalid 2.5 2.5 ns t kqlz (2,3) clock high to output low-z 2.5 2.5 ns t kqhz (2,3) clock high to output high-z 3.8 4.0 ns t oeq output enable to output valid 3.2 3.4 ns t oeqx (2) output enable to output invalid 2.5 2.5 ns t oelz (2,3) output enable to output low-z 0 0 ns t oehz (2,3) output disable to output high-z 3.5 3.5 ns t as address setup time 1.5 1.5 ns t ss address status setup time 1.5 1.5 ns t ws read/write setup time 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 ns t av s address advance setup time 1.5 1.5 ns t ds data setup time 1.5 1.5 ns t ah address hold time ? 0.5 0.5 ns tw h write hold time 0.5 0.5 ns t sh address status hold time 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 ns t av h address advance hold time 0.5 0.5 ns t dh data hold time 0.5 0.5 ns t pds zz high to power down 2 2 cyc t pus zz low to power down 2 2 cyc notes: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
integrated silicon solution, inc. 17 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a read/write?cycle? timing single read flow-through single write high-z high-z data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeqx t kq t oehz t kqx t kqhz t ds t dh t kqhz t kqlz t kq t kq t kqx
18 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a write?cycle? timing single write data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce1 inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr 2 write 2c 2d 2b 2a
integrated silicon solution, inc. 19 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a snooze?mode? timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z snooze?mode?electrical? characteristics ? symbol? parameter ? conditions? min. ? max. ? unit ? i sb 2 current during snooze mode zz vih 60 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to snooze current 2 cycle t rzzi zz inactive to exit snooze current 0 ns
20 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a ordering? information?(v dd ?=?3.3v/v ddq ?=?2.5v/3.3v) commercial ? range: ?0c?to?+70c ? confguration? access? time? order ? part?number? package 128kx32 6.5 is61lf12832a-6.5tq 100 tqfp is61lf12832a-6.5b2 119 pbga is61lf12832a-6.5b3 165 pbga 128kx32 7.5 is61lf12832a-7.5tq 100 tqfp is61lf12832a-7.5b2 119 pbga is61lf12832a-7.5b3 165 pbga ? 128kx36 6.5 is61lf12836a-6.5tq 100 tqfp is61lf12836a-6.5b2 119 pbga is61lf12836a-6.5b3 165 pbga 128kx36 7.5 is61lf12836a-7.5tq 100 tqfp is61lf12836a-7.5b2 119 pbga is61lf12836a-7.5b3 165 pbga 256kx18 6.5 is61lf25618a-6.5tq 100 tqfp is61lf25618a-6.5tql 100 tqfp, lead-free is61lf25618a-6.5b2 119 pbga is61lf25618a-6.5b3 165 pbga 256kx18 7.5 is61lf25618a-7.5tq 100 tqfp is61lf25618a-7.5b2 119 pbga is61lf25618a-7.5b3 165 pbga
integrated silicon solution, inc. 21 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a ordering? information?(v dd ?=?3.3v/v ddq ?=?2.5v/3.3v) industrial? range: ?-40c?to?+85c ? confguration? access? time? ord er? part?number? package 128kx32 6.5 is61lf12832a-6.5tqi 100 tqfp is61lf12832a-6.5b2i 119 pbga is61lf12832a-6.5b3i 165 pbga 128kx32 7.5 is61lf12832a-7.5tqi 100 tqfp is61lf12832a-7.5tqli 100 tqfp, lead-free is61lf12832a-7.5b2i 119 pbga is61lf12832a-7.5b3i 165 pbga ? 128kx36 6.5 is61lf12836a-6.5tqi 100 tqfp is61lf12836a-6.5tqli 100 tqfp, lead-free is61lf12836a-6.5b2i 119 pbga is61lf12836a-6.5b3i 165 pbga 128kx36 7.5 is61lf12836a-7.5tqi 100 tqfp is61lf12836a-7.5tqli 100 tqfp, lead-free is61lf12836a-7.5b2i 119 pbga is61lf12836a-7.5b3i 165 pbga 256kx18 6.5 is61lf25618a-6.5tqi 100 tqfp is61lf25618a-6.5b2i 119 pbga is61lf25618a-6.5b3i 165 pbga 256kx18 7.5 is61lf25618a-7.5tqi 100 tqfp is61lf25618a-7.5tqli 100 tqfp, lead-free is61lf25618a-7.5b2i 119 pbga is61lf25618a-7.5b3i 165 pbga automotive ? range: ?-40c?to?+125c ? confguration? access? time? order ? part?number? package 128kx32 7.5 is64lf12832a-7.5tqa3 100 tqfp ? is64lf12832a-7.5tqla3 100 tqfp, lead-free 128kx36 7.5 is64lf12836a-7.5tqa3 100 tqfp is64lf12836a-7.5b3la3 165 pbga, lead-free 256kx18 7.5 is64lf25618a-7.5tqa3 100 tqfp
22 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a ordering? information?(v dd ?=?2.5v?/v ddq ?=?2.5v) commercial ? range: ?0c?to?+70c ? confguration? access? time? order ? part?number? package 128kx36 6.5 is61vf12836a-6.5tq 100 tqfp is61vf12836a-6.5b2 119 pbga is61vf12836a-6.5b3 165 pbga 128kx36 7.5 is61vf12836a-7.5tq 100 tqfp is61vf12836a-7.5b2 119 pbga is61vf12836a-7.5b3 165 pbga 256kx18 6.5 is61vf25618a-6.5tq 100 tqfp is61vf25618a-6.5b2 119 pbga is61vf25618a-6.5b3 165 pbga 256kx18 7.5 is61vf25618a-7.5tq 100 tqfp is61vf25618a-7.5b2 119 pbga is61vf25618a-7.5b3 165 pbga industrial? range: ?-40c?to?+85c ? confguration? access? time? order ? part?number? package ? 128kx36 6.5 is61vf12836a-6.5tqi 100 tqfp is61vf12836a-6.5b2i 119 pbga is61vf12836a-6.5b3i 165 pbga 128kx36 7.5 is61vf12836a-7.5tqi 100 tqfp is61vf12836a-7.5b2i 119 pbga is61vf12836a-7.5b3i 165 pbga 256kx18 6.5 is61vf25618a-6.5tqi 100 tqfp is61vf25618a-6.5b2i 119 pbga is61vf25618a-6.5b3i 165 pbga 256kx18 7.5 is61vf25618a-7.5tqi 100 tqfp is61vf25618a-7.5b2i 119 pbga is61vf25618a-7.5b3i 165 pbga automotive ? range: ?-40c?to?+125c ? confguration? access? time? order ? part?number? package 128kx32 7.5 is64vf12832a-7.5tqla3 100 tqfp, lead-free 128kx36 7.5 is64vf12836a-7.5tqa3 100 tqfp 256kx18 7.5 is64vf25618a-7.5tqa3 100 tqfp
integrated silicon solution, inc. 23 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a
24 integrated silicon solution, inc. rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 1. controlling dimension : mm . note : 2. reference document : jedec ms-028 10/02/2008 package outline
integrated silicon solution, inc. 25 rev.? f 09/28/2010 is61(64)lf12832a, ?is61(64)lf12836a, ?is61(64)lf25618a is64vf12832a, ??is61(64)vf12836a, ??is61(64)vf25618a 1. controlling dimension : mm . note : package outline 08/28/2008

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